Cadence CEO: AI Agents Are Driving More Base Tool Usage, Not Less — And the IP Business Is Finally World-Class
Bank of America Global Technology Conference, June 3, 2026 — Cadence Design Systems CEO Anirudh Devgan makes the bull case for why AI disruption fears are fundamentally misplaced
The debate over whether AI will cannibalize EDA software demand has been a persistent overhang on Cadence Design Systems. CEO Anirudh Devgan used his appearance at the Bank of America Global Technology Conference on Wednesday to deliver the most direct rebuttal yet — and the logic is worth understanding carefully, because it reshapes how investors should think about both the risk and the opportunity.
Why Agentic AI Actually Increases Base Tool Consumption
The core insight Devgan shared is counterintuitive but grounded in observed customer behavior. When AI agents write RTL code autonomously, those agents still need to verify that the code is correct. That verification runs through Cadence's Xcelium simulation and Jasper formal verification tools. The result, as Devgan explained, is that agentic workflows are generating more usage of base tools, not less. He pointed directly to NVIDIA as the proof point, noting that Jensen Huang highlighted Cadence at COMPUTEX: "When ChipStack is writing RTL, it actually uses more Jasper and more Xcelium. So actually, the number of base tool usage is going up versus a non-agentic world."
His framework for why this must be true rests on what he calls the three-layer cake — the agentic AI layer on top, the ground truth tools in the middle, and compute and data at the base. For tasks that are simple, an LLM might handle the whole job. But chip design is not simple. "In our case, we are not even like a microwave. We are like a nuclear reactor. So when a bunch of robots come, they're not going to build nuclear reactors. They're going to use nuclear reactors in a more effective way."
The second element of the bull case is the exponential nature of the underlying workload. TSMC's own road map, as Devgan noted from a recent presentation, shows that transistor counts in chip-plus-package systems will increase 48x to 50x over the next five years. One major customer has told Cadence that each successive chip generation requires twice as many engineers — a headcount trajectory that is simply unrealizable. AI agents blunt that curve and make the designs possible at all. In a world where the workload is merely flat, more automation would mean fewer tool licenses. In Cadence's world, where demand is exponential, automation is what makes the market function.
A New TAM, Not Just an Efficiency Tool
Devgan was clear that the agentic products — ChipStack for RTL, ViraStack, and InnoStack — represent genuine TAM expansion, not just a repackaging of existing licenses. "If we are having tools to write RTL, there were no tools like that. So it's a new TAM to buy." He described the commercial logic as multiplicative: the new agentic layer generates revenue in its own right, and then drives incremental consumption of the base tool stack on top of that.
Engagement with these agentic flows is already broad. Devgan cited Qualcomm, MediaTek, and a range of other large customers as active participants in ChipStack deployments, and noted that demand spans traditional semiconductor companies, hyperscalers, analog and mixed-signal houses, and systems companies simultaneously.
IP: Honest About the Past, Confident About Now
Perhaps the most candid section of the conversation concerned Cadence's IP business, which had historically lagged peers. Devgan did not deflect. "I also intentionally in the beginning didn't invest as much in IP, just to be honest, because we wanted to make sure that we are good in EDA first." He spent his first four years as CEO prioritizing EDA, on the thesis that everything else would follow from a position of core tool strength.
The IP strategy that has since emerged is deliberately narrow. Cadence is focused on five star IPs at advanced nodes: DDR memory subsystems, PCIe, UCIe (chip-to-chip interconnect), HBM, and SerDes. The rationale is that the largest customers buy best-in-class and are not interested in a broad but mediocre portfolio. Winning with the largest players creates a pull effect for the rest of the market. The key variable, Devgan argued, is R&D team quality. "Finally, in IP, I finally believe that the team is world-class. It wasn't world-class before." With standardized interfaces, PPA — performance, power, and area — is the primary competitive differentiator, and Cadence now believes it has closed that gap.
The structural tailwinds amplifying this repositioning include chiplet disaggregation, which makes interconnect IP such as UCIe more strategically valuable, and a broadening of the customer base to include Intel and Samsung, which Devgan characterized as meaningful new opportunities the company had limited access to historically.
Internal Productivity as a Proof Point — and a Margin Signal
Devgan offered an unusually specific internal productivity target that has direct implications for Cadence's margin trajectory. The company's 3,000-person IP group is being run through its own agentic tools, with a stated goal of at least a 2x productivity improvement. The math he laid out: a 30% reduction in headcount per project combined with a 30% reduction in schedule yields a 0.7 times 0.7 multiplier, or roughly 2x. "Some customers told me they want 0.5 times 0.5 — so that's like 4x."
He noted this is already showing up in financials. Incremental operating margins are running at 60%, well above the company's reported operating margin of approximately 44% to 45%. He described the broader workforce of roughly 15,000 — including 4,000 customer-facing application engineers and 7,000 in core R&D — as beneficiaries of standard AI coding tools like Claude and Codex alongside the proprietary agentic stack. The implication is that operating leverage is structural and ongoing, not a one-time event.
Design Activity and the Competitive Environment
Devgan described the current design environment as the strongest he has seen, driven by three concurrent forces. First, hyperscaler chip design activity has re-accelerated, with Google's custom silicon success and Chinese vertically integrated players — he cited Xiaomi specifically as "very impressive" with its own chips, cars, robots, and LLM models — spurring competitive responses across the industry. Second, the traditional semiconductor end markets covering analog, memory, and industrial have begun recovering. Third, Cadence now has active opportunities with customers it had limited penetration with previously.
On the question of whether rising TSMC pricing and complexity could cap design starts, Devgan was dismissive. "The value is very high," he said, pointing to the economics of verticalization as the more powerful driver. Companies like BYD, Nio, and XPeng are all Cadence customers, and their design ambitions are expanding, not contracting.
Physical AI: Still 3 to 7 Years, But the Designs Are Starting Now
Devgan has been making the physical AI call for several years and acknowledged that it has taken time to gain credibility. His view remains that the market is 3 to 7 years out from full realization, but that the design cycle means customer engagement is already underway. He named Tesla, Rivian, BYD, Nio, XPeng, and Xiaomi as active participants in what he sees as a structural build-out of silicon for autonomous systems and robotics. He also flagged analog players like ADI and TI as early beneficiaries.
His portfolio argument is that Cadence's positioning across both data center AI and physical AI provides a degree of resilience that purely volume-driven semiconductor businesses lack. "Even if things turn south a little bit, it should still be good for Cadence Design." The physical AI focus, in his framing, is about not missing the next wave while executing on the current one.
Competitive Positioning
Asked directly about the competitive dynamic with Synopsys, Devgan made no effort at diplomatic neutrality. He argued Cadence holds an advantage in core EDA by virtue of being the only vendor with full coverage across analog, digital, verification, and packaging — a breadth he said is particularly evident in the TSMC ecosystem where PPA requirements are most demanding. On IP, share gains are ongoing. On hardware emulation, the Palladium platform is described as a unique offering. "What I tell investors is, yes, you can invest in both, but just invest more in Cadence." When pressed on whether that was objective, he added: "It's also true, right, if you go back and look at the last 5 years."
Cadence has delivered approximately 15% revenue CAGR over the past five years through a mixed environment. The combination of a stronger design backdrop, agentic TAM expansion, IP share gains, and internal productivity leverage gives Devgan the basis for arguing that current momentum is durable — though he was careful to note the company guides one year at a time and does not make multi-year commitments publicly. The environment, as he put it, is "probably the best it has been."