Micron Lays Out Planar DRAM Path Through 1-Eta, Rejects 4F2 and Introduces Vertical HBM and Edge Inference Memory as New Product Platforms
Technology and Product Leadership Webinar, October 21, 2026
Micron used a technology webinar to make two points investors can act on. First, the company says it sees a clear planar DRAM scaling path for several more nodes, with 3D DRAM positioned as a parallel track to be introduced on cost and performance grounds rather than on a fixed date. Second, it is broadening its AI memory portfolio beyond today's HBM into vertical HBM, vertical edge inference memory and two classes of AI-specific NAND. President and Chief Technology and Products Officer Scott DeBoer said the company has "more confidence in the next several years of scaling on both DRAM and NAND than we have in quite some time." No financial guidance was provided.
Micron Rejects 4F2 and Frames 3D DRAM as a Business-Timed Transition
The most contested technical question was 4F2 cell architecture, which some competitors are reportedly pursuing. DeBoer was unusually direct. Micron invented 4F2, has prototyped it for roughly two decades, and has chosen not to pursue it. His argument is that bit density is set by capacitor pitch, not by the cell layout beneath it. "It's a bit of a myth that 4F2 actually provides anything versus 6F2. It's the capacitor pitch that defines the DRAM," he said, adding that parts of the 4F2 debate are "smoke and mirrors." He conceded that 4F2 can be built a few nodes back, at higher cost and complexity, but said that beyond today's nodes "it's physics," and that the fundamental scaling problems "ultimately will lead to 3D DRAM coming in, instead of 4F2."
On 3D DRAM, Micron said the technology is on the road map between 1-zeta and 1-eta but is a parallel path. Timing "will depend on Micron business decisions," and the company will implement it when it is ideal for cost, complexity and device performance. DeBoer acknowledged that DRAM is "nearing atomic limits," yet said Micron has confidence in several more planar nodes. Citi's Atif Malik singled out the 3D DRAM versus 4F2 update as the key takeaway. Investors should note that the absence of a 3D DRAM date leaves the transition timing unquantified, and that it hinges on a management judgment about cost.
DRAM Road Map: 1-Delta Ramps in the Second Half of 2027
The 1-gamma node, the first at Micron to use EUV, is in high-volume manufacturing and will be the main running node for the next year. The 1-delta node, being developed in Boise and slated for U.S. manufacturing among other sites, is targeted to ramp in the second half of 2027. Micron called it its fifth consecutive industry leadership node. It should deliver a mid-20s percentage bit density improvement, with a design focus on cost and on optimization for HBM5, vertical HBM and vertical edge inference memory. The 1-epsilon node, which uses wafer bonding, is "well underway," and early development is under way on 1-zeta and 1-eta, combining high-NA EUV and new materials.
DeBoer also said Micron will run multiple CMOS variants within a single node, tuned for LP or HBM use, and projected about a 10x improvement in drive current at a given leakage from 2020 through 2030. On products, LPDDR6 is targeted at 35% better power than LP5, DDR6 at 2x the bandwidth of DDR5, and a 1-terabyte RDIMM is planned as the successor to the 512-gigabyte DDR5 RDIMM already sampled.
Vertical HBM Adds a New Tier, and the Trade Ratio Keeps Rising
Beyond standard and custom HBM, Micron is adding vertical HBM, which places memory directly on top of the processor. DeBoer said the benefit is bandwidth and power that "can't really be done in a different way." He expects most systems to pair HBM5E around the edge of the XPU with vertical HBM on top. The constraint is thermal. Stacking many dies over a hot processor is difficult, so capacity will scale more slowly than bandwidth, at least initially. Micron already uses a heat spreader that serves as "a chimney for heat" above the hottest part of the HBM base die.
The supply implication is important. DeBoer said trade ratios, the number of wafers needed per bit of HBM versus standard DRAM, "continue to increase" across HBM, vertical HBM and vertical edge inference memory. Vertical HBM carries a very high ratio both from stacking and because its much larger I/O count reduces die per wafer. That points to continued pressure on DRAM bit supply, which fits his remark that Micron does not "see a time when [memory] comes into balance" in the next two years, a view he attributed to CEO Sanjay Mehrotra.
On the base die, Micron confirmed it will use foundry nodes for both standard JEDEC and custom HBM base dies, without naming the node. It said HBM4 did not need an advanced process, "some competitors used it. Our HBM4 didn't," but HBM4E does require more advanced CMOS for speed and power. Vertical HBM will keep advanced nodes in the base die, with more functionality offloaded from the GPU. HBM4 is in high-volume manufacturing, with one stack delivering 2.8 terabytes per second. Hybrid bonding is described as essential for interconnect density, not just thermals, though it still needs to mature for high-volume use.
Edge Inference Memory Takes On Processing-in-Memory
For physical AI and the edge, Micron is developing vertical edge inference memory, which stacks LPDRAM on a logic base die. Asked about peers' processing-in-memory approaches, DeBoer said Micron has PIM solutions "in flight and in discussion with customers" as well. He argued that vertical EIM delivers substantially higher bandwidth and capacity, and can reach lower power through the base die. The spectrum runs from sub-picojoule-per-bit edge devices up to HBM. Because the core technology is largely common, differences come down to design and segmentation. This is a platform play, though no customer or revenue timing was given.
NAND: Gen11 Doubles Density and Introduces AI-Class Variants
Micron is skipping a node number, moving from G9 to G11, and calls it the world's most advanced NAND. It offers double the bit density of G9, a 1.5x I/O speed target, lower data transfer energy, wafer-on-wafer bonding and more than 400 layers. It also ramps in the second half of 2027. Layer specifics will come closer to launch.
Two AI-class NAND directions were laid out. High-IOPS NAND uses SLC-based designs in small blocks for very fast storage and is a priority over the next couple of years. High-bandwidth NAND uses TSV-stacked NAND with a logic base die and is costlier, requiring customer partnership. DeBoer said it would sit near compute but not "along the short line of the GPU as we don't think that has merit." Micron also cited first-to-market PCIe Gen6 data center SSDs in mass production.
AI in Development Cuts Design Cycles by Half
Micron said that AI tools cut the silicon-to-tape-out time of its new data center SSD controller by 50%, and the time to develop an entire data center SSD by 60%, using AI-generated firmware, root cause analysis and agents. DeBoer described this as central to handling a growing volume of customer-specific programs. These are two examples, not a company-wide metric.
Long-Horizon R&D and Customer Co-Design
DeBoer pointed to a stepped-up investment posture: a larger Micron Ventures commitment, an advanced lithography effort at Albany NanoTech focused on high-NA EUV for DRAM, and a previously announced $10 billion over 10 years for Micron Research Labs. On customers, he described a co-design model "very different than the way we interacted with customers even 3 or 4 years ago," citing a white paper released the same morning with Meta on LPDDR6 for the data center and a partnership with WEKA, a company Micron first backed through its venture fund.
Memory Content Per System Not Expected to Fall
Responding to Bank of America's Vivek Arya on concerns that memory is becoming half or more of the bill of materials and that inference may need less DRAM than training, DeBoer did not concede any change. Customers will optimize around minimum system requirements, and edge and small-model products will have different configurations, but "more memory does equal better system performance." This is a supplier's view, and the webinar offered no data on how customers are actually trading off cost against content.