Micron Technology: Supply Structurally Constrained for Years, HBM4 Ramp Outpacing Expectations
J.P. Morgan 54th Annual Global Technology Conference, May 20, 2026
Micron Technology's head of global operations, Manish Bhatia, delivered a notably bullish operational update at J.P. Morgan's annual technology conference, offering the clearest picture yet of how deeply structural the memory supply shortage has become and how aggressively Micron is moving to capitalize on it. The headline message was unambiguous: supply cannot catch up to demand "for the foreseeable future," and the company expects tightness in HBM, DRAM, and NAND to persist well beyond calendar year 2026. What makes this conference stand out is the specificity around the HBM4 production ramp, new fab timelines, and the emerging strategic customer agreement framework — all of which have meaningful implications for Micron's revenue trajectory and margin profile over the next several years.
HBM4 Ramp Running Twice as Fast as HBM3E
The single most important operational data point disclosed at the conference is that Micron's HBM4 production ramp is proceeding at twice the pace of the HBM3E 12-high ramp from last year — itself a ramp Bhatia described as one the team was "very, very pleased with." Yields on HBM4 are also improving faster than the prior generation, consistent with guidance given at the last earnings call. HBM4 is built on Micron's 1-beta DRAM platform with an in-house optimized base die, and volume shipments into NVIDIA's Vera Rubin GPU platform began in March. The combination of faster ramp velocity and better yield trajectory is a meaningful positive relative to market expectations, particularly given that some peers have reportedly encountered performance qualification issues on HBM4.
On HBM4E — the next inflection due to ramp in calendar 2027 — Bhatia confirmed that development is well underway and that the first product will be a JEDEC-standard part, built on the 1-gamma DRAM node with a TSMC-sourced logic die. This is an important clarification: the first HBM4E silicon will not carry the complexity premium of a customer-specific base die design. Customized variants are in active discussion with customers, but investors should not assume immediate margin uplift from customization at the outset of the HBM4E cycle. The TSMC relationship for both the JEDEC and customized base dies was confirmed. On pricing for customized variants, Bhatia was direct: "Our customers will be willing to pay for that," citing the engineering complexity involved across design, core process, and advanced packaging as justification for premium pricing.
The Structural Supply Problem Is Getting Worse, Not Better
Bhatia laid out a detailed and persuasive case for why memory supply will remain structurally constrained. Technology node transitions for both DRAM and NAND are delivering diminishing productivity gains — fewer bits per wafer per node than transitions of prior generations. Layered on top of this for DRAM is the HBM structural shift: because HBM die sizes are larger, it requires more than 3x as many wafers to deliver the same number of bits compared to standard DRAM, and critically, that trade ratio continues to grow as the industry progresses from HBM3E to HBM4 to HBM4E. The implication is that greenfield clean room capacity — full fab lines rather than incremental equipment upgrades — is a necessity, and that takes years to build and equip.
J.P. Morgan's Harlan Sur noted that Micron had previously told investors that key customers could only secure 50% to two-thirds of their bit demand requirements in the medium term. Bhatia did not refute this figure and instead reinforced it, noting that demand drivers are "getting even stronger" while supply remains extremely difficult to increase. The gap between what customers need and what the industry can supply does not appear to have narrowed.
A Significant Wave of Capacity Coming — But Not Until Late 2027 and Beyond
Bhatia provided the most comprehensive public update yet on Micron's multi-site capacity expansion program. In Taiwan, the acquired Powerchip Semiconductor Tongluo site — a transaction that closed ahead of schedule — is on track for leading-edge DRAM production output in the second half of calendar 2027. Construction of a twin fab immediately adjacent to the Tongluo site is beginning this summer, with the combined footprint intended to function as a mega-cluster site just 20 minutes from existing Taichung operations. In Idaho, the company pulled in the Idaho 1 wafer output target to mid-2027 from second half of 2027, and Idaho 2 ground preparation is already underway with expected wafer output in late calendar 2028. In New York, the facility is ahead of schedule with concrete pouring expected later this year. In Singapore, an HBM-dedicated facility broken ground at the start of calendar 2025 is on track for production contribution in calendar 2027, and a new NAND fab was broken ground on earlier this year.
The breadth of this expansion is impressive, but investors should be clear-eyed: virtually none of this new capacity enters production before mid-to-late 2027, meaning near-term supply relief is not coming from greenfield. The company's ability to satisfy demand over the next four to six quarters rests entirely on yield improvement, productivity gains, and technology migration on existing installed base.
1-Gamma DRAM and Gen9 NAND Crossing Over on Schedule, With EUV Delivering
Bhatia confirmed that both 1-gamma DRAM and Gen9 NAND are on track to cross over as the majority of Micron's respective bit output mixes by the middle of this year. Both nodes are ramping faster in yield than prior generations. EUV, introduced for the first time at the 1-gamma node, is performing well, with better-than-expected tool availability and performance from ASML. As a result, Micron has already concluded a multiyear EUV supply agreement with ASML covering multiple future technology generations and capacity plans — a signal that EUV deployment will accelerate meaningfully at 1-delta and beyond. Bhatia expects 1-gamma to become the highest-volume DRAM node in the company's history by total wafer output.
Strategic Customer Agreements Expanding, But Details Remain Scarce
At the March earnings call, Micron disclosed its first Strategic Customer Agreement — a five-year deal with a large, unnamed customer covering volume, pricing, and duration commitments. At this conference, Bhatia confirmed that "meaningful progress" has been made with additional SCA customers and that NAND and SSD SCAs are also in progress, but declined to provide specifics on how many agreements have been signed or what percentage of the next twelve months' bit shipments are now covered. An update is promised at a future date. The strategic logic is straightforward: with multi-year fab construction cycles, having long-term committed volume and pricing helps Micron align greenfield capacity decisions with real demand signals — reducing the planning risk that has historically made memory a boom-bust business.
Data Center SSD: Share Gains Continuing, and NAND's Strategic Role Is Expanding
Micron's enterprise SSD franchise has grown from roughly 5-7% global market share in 2022 to approximately 15% exiting last year, making it the third-largest player globally. The company's PCIe Gen5 9550 platform is performing well, and the Gen6 9650 — built on Gen9 NAND and the first PCIe Gen6 SSD to market — has earned a position on NVIDIA's STX reference platform. Bhatia credited over a decade of deliberate investment in in-house ASIC controller design and firmware development for this trajectory, explicitly noting that the goal was never to produce "me-too" products but to target performance leadership. He indicated the team expects continued share gains.
On the broader architectural evolution, Bhatia discussed both CXL-based DRAM pooling and high-bandwidth flash as emerging technologies addressing AI inferencing workloads, particularly KV cache offloading as context windows continue to grow. He noted that context windows have expanded 30x per year, driven by the need for greater accuracy in AI outputs, and that NAND's role is increasingly about improving model accuracy rather than just storing data. While high-bandwidth flash was acknowledged as an interesting technology with meaningful attributes, Bhatia was careful not to commit to it as a primary strategic priority, framing it instead as one of many innovation vectors across the memory hierarchy where Micron's broad portfolio positions it well.
Financial Outlook: Record FCF Imminent, Balance Sheet at Peak Strength
Bhatia opened with a brief but pointed financial update, noting that Micron's financial outlook "has strengthened since our last earnings call" and that the company is on track for "another substantial record free cash flow" in fiscal Q3. All three major credit rating agencies have upgraded Micron this year — a signal of balance sheet strength that is meaningful for a company with the capital intensity of Micron's current expansion program. When pressed on whether the May quarter has tracked above the March guidance midpoint of $33.5 billion in revenue, 81% gross margins, and approximately $19 in earnings power, Bhatia declined to provide an intra-quarter update, noting the quarter closes in a couple of weeks. The refusal was not surprising, but the opening commentary about a "strengthened" outlook since the last call and pricing having "played out" suggests the quarter is not running below expectations.
Micron Technology Deep Dive
Business Model and Monetization Engine
Micron Technology designs, develops, and manufactures highly advanced memory and storage products. The core monetization engine is divided into two primary technology pillars: Dynamic Random Access Memory and NAND Flash. Dynamic Random Access Memory, which typically accounts for roughly 70% to 75% of total revenues, serves as the high-speed working memory for central and graphics processing units. NAND Flash, comprising the remainder of the business, provides non-volatile, long-term data storage utilized in solid-state drives for data centers, mobile devices, and consumer electronics. Historically, Micron operated strictly as a commodity manufacturer navigating brutal boom-and-bust cycles dictated by spot market pricing. Today, the business model has fundamentally evolved. Driven by the immense bandwidth requirements of artificial intelligence infrastructure, Micron is transitioning from a transactional component supplier into a strategic platform partner. The company now increasingly monetizes its advanced silicon through long-term, multi-year supply agreements featuring volume commitments and price collars. This structural evolution shifts the revenue profile away from extreme cyclicality toward more predictable, high-margin cash flows, effectively capturing a massive premium for the complex packaging and engineering required to feed modern computational bottlenecks.
Value Chain: Customers, Competitors, and Suppliers
The value chain surrounding Micron is highly concentrated at every level. The customer base is currently dominated by data center hyperscalers, including Amazon, Microsoft, Google, and Meta, alongside the premier artificial intelligence accelerator designers such as Nvidia and AMD. These entities dictate the technological roadmap and command the lion's share of high-margin memory allocation. Secondary end markets include traditional PC manufacturers like Dell and HP, smartphone titans such as Apple, and a fragmented array of automotive and industrial clients. On the competitive front, Micron operates within a rigid oligopoly. In the Dynamic Random Access Memory market, its sole rivals are the South Korean conglomerates Samsung Electronics and SK Hynix. The NAND landscape is slightly wider but equally cutthroat, featuring Samsung, SK Hynix, Kioxia, and Western Digital. To manufacture these sub-nanometer architectures, Micron depends entirely on a monopolistic and oligopolistic supply base. The company is completely reliant on ASML for Extreme Ultraviolet lithography machines to print advanced patterns on silicon wafers. Furthermore, Micron requires highly specialized etch and deposition tools from Lam Research, materials engineering systems from Applied Materials, and precision coating equipment from Tokyo Electron to execute the complex vertical scaling necessary for high-layer NAND and advanced memory nodes.
Market Share Dynamics
The contemporary market share layout reflects a highly disciplined industry prioritizing profitability over volume. As of the first half of 2026, SK Hynix leads the broader Dynamic Random Access Memory market with roughly 34% share, propelled by its early first-mover advantage in the artificial intelligence memory supercycle. Samsung holds approximately 35% of standard memory, though its grip has fluctuated significantly amid operational pivots. Micron confidently controls the remaining 21% to 22% of the market. However, the most critical battleground is the ultra-high-margin High-Bandwidth Memory segment. Here, SK Hynix commands a dominant 62% of global volume. Micron has executed a highly aggressive catch-up strategy to seize approximately 21% of this premium market, notably leapfrogging Samsung, which currently languishes at 17%. In the NAND flash segment, Samsung maintains the lead with roughly 29% market share, followed by SK Hynix at 19% and Kioxia at 16%. Micron deliberately limits its NAND exposure to 12%, an intentional strategic choice to avoid the most severely commoditized tiers of data storage. By willingly ceding low-end standard memory share across both segments, Micron has concentrated its wafer allocation purely on the highest revenue-per-bit products.
Competitive Advantages
Micron possesses a multi-layered competitive moat built on technological density, advanced packaging execution, and geopolitical alignment. The company's primary advantage stems from its successful node jump strategy, allowing it to achieve parity and arguably outright leadership in the 1-beta and 1-gamma Extreme Ultraviolet manufacturing processes. This base silicon excellence is compounded by Micron's mastery of Through-Silicon Via packaging, a complex vertical stacking architecture that is yielding exceptionally well in mass production. Furthermore, Micron has differentiated itself by offering a fully integrated platform rather than standalone chips. It stands as the only memory supplier globally qualified across the entire triad of next-generation infrastructure, including High-Bandwidth Memory, PCIe Gen6 solid-state drives, and advanced memory modules for the latest artificial intelligence accelerators. Beyond sheer engineering, Micron holds a unique geopolitical advantage. As the undisputed domestic champion of semiconductor memory in the United States, the company is heavily insulated by federal support. Leveraging the CHIPS Act, Micron is executing massive $200 billion long-term fabrication expansions in New York and Idaho, presenting Western hyperscalers with a secure, geographically diversified supply chain entirely isolated from Asian geopolitical flashpoints.
Industry Dynamics: Opportunities and Threats
The memory industry is currently riding an unprecedented structural supercycle. Because memory bandwidth has replaced raw compute as the absolute bottleneck for training and inferencing Large Language Models, suppliers wield immense pricing power. This dynamic presents massive near-term opportunities, particularly given the acute supply constraints defining 2026. A highly relevant catalyst is the historic labor action currently unfolding at Samsung, where an unprecedented general strike commencing in May 2026 threatens to sideline over 64% of its semiconductor workforce. With 2026 industry capacity already fully booked, even a minor disruption to the 3% to 4% of global supply impacted by this strike exerts exponential upward pressure on contract pricing, funneling immediate margin expansion directly to SK Hynix and Micron. Conversely, the primary industry threat lurks at the end of the decade. While the shift toward binding multi-year contracts smooths current volatility, it cannot alter the fundamental physics of capital expenditure. The vast, subsidized fabrication plants being constructed across the United States, South Korea, and Japan are slated to flood the market with aggregate output by 2028 and 2029. If artificial intelligence infrastructure scaling plateaus as these facilities come online, the industry faces a severe risk of structural oversupply and a reversion to destructive cyclical pricing.
Next-Generation Growth Drivers
Micron's forward growth trajectory is entirely dependent on its ability to execute the next wave of high-density interconnects. The most critical revenue driver is the migration to the HBM4 standard. Having commenced high-volume production of the 36-gigabyte 12-high stack in early 2026, Micron has directly co-designed its architecture to seamlessly integrate with Nvidia's Vera Rubin graphical processing platform. Beyond the accelerator market, the commercialization of Compute Express Link memory modules represents a massive, untapped frontier. This technology allows data centers to create composable, shared pools of memory independent of individual server constraints, effectively dismantling traditional server architecture and driving vast new demand for high-capacity memory arrays. In edge computing and consumer markets, the adoption of Low Power Compression Attached Memory Module 2 and LPDDR5X running at speeds exceeding 9600 megabits per second are critical enablers for the incoming wave of artificial intelligence-enabled personal computers and smartphones. Concurrently, in the storage domain, Micron's progression beyond 232-layer architectures toward 300-plus layer 3D NAND is drastically lowering the cost-per-bit, positioning the company to capture the massive data-lake storage requirements generated by multimodal artificial intelligence models.
The Disruptive Threat of New Entrants
The global memory oligopoly faces its most credible disruptive threat in decades from Chinese state-backed entities, specifically ChangXin Memory Technologies and Yangtze Memory Technologies. Propelled by billions in sovereign capital and an imperative for technological self-sufficiency, ChangXin Memory Technologies has aggressively broken out to capture approximately 7.6% of the global market, with stated capacities targeting up to 13%. Operating under severe geopolitical constraints and lacking access to cutting-edge Extreme Ultraviolet lithography, these entrants suffer from highly uncompetitive yield rates estimated between 40% and 50%. However, state subsidies absorb these catastrophic inefficiencies, allowing them to ruthlessly flood the market with consumer-grade legacy memory. This massive influx of subsidized silicon has effectively destroyed the profitability floor for older generations of memory. While ChangXin Memory Technologies and Yangtze Memory Technologies pose no immediate threat to the high-bandwidth, advanced node architectures utilized in data centers, their dominance at the low end acts as an intense forcing function. It mandates that Western and South Korean producers permanently abandon commoditized consumer tiers and accelerate their capital migration strictly toward advanced packaging and leading-edge nodes where lithography barriers prevent Chinese replication.
Management Track Record
Over the past several years, CEO Sanjay Mehrotra has orchestrated one of the most successful strategic turnarounds in the semiconductor sector. Historically viewed as the perennial technology laggard of the memory oligopoly, management systematically rebuilt Micron's engineering culture to prioritize execution and capital efficiency over brute-force market share. This disciplined philosophy culminated in the highly effective transition to 1-beta and 1-gamma nodes, a feat that allowed Micron to leapfrog legacy competitors and capture roughly 21% of the ultra-premium high-bandwidth memory market from a standing start. Management's operational leverage and pricing discipline were undeniably validated in early 2026, as the company reported an exceptional $23.86 billion in quarterly revenue paired with $12.20 in earnings per share. Crucially, the executive team utilized this period of extreme leverage to alter the business model itself, securing comprehensive multi-year volume agreements that attempt to structurally derisk the company's future cash flows. By maintaining intense cost discipline, achieving gross margins exceeding 74% during the cycle peak, and aggressively returning capital through billions in repurchases and elevated dividends, management has demonstrated a profound mastery of both technological execution and shareholder value creation.
The Scorecard
Micron Technology has successfully transcended its legacy as a highly cyclical commodity manufacturer to become an indispensable infrastructural pillar of the global artificial intelligence economy. By securing a commanding position in the high-bandwidth memory oligopoly and leveraging its status as the premier United States-based manufacturer, the company has heavily insulated itself against near-term demand shocks. The structural shift toward multi-year pricing agreements, combined with acute supply constraints exacerbated by ongoing competitor labor disruptions, provides unprecedented financial visibility and profitability through the medium term. Furthermore, aggressive execution on next-generation architectures like advanced node memory and composable compute solutions cements its platform-level integration with the world's largest hyperscalers.
However, the long-term structural risks inherent to the semiconductor capital expenditure cycle remain firmly intact. The massive influx of state-subsidized capacity from Chinese entrants is permanently commoditizing the low-end memory market, leaving leading-edge nodes as the sole sanctuary for margin expansion. As the industry readies massive capacity additions slated for the end of the decade, the specter of oversupply continues to loom ominously over the sector. Market participants must carefully weigh the current era of exceptional management execution and hyper-profitability against the inevitable normalization of artificial intelligence infrastructure spending and the inescapable physics of memory market cyclicality.