TSMC Lifts 2026 CapEx to $64 Billion and Adds $100 Billion Arizona Bet as AI Demand Outstrips Supply "By a Very Big Gap"
Q2 2026 earnings call, July 16, 2026
Taiwan Semiconductor Manufacturing Company used its second-quarter earnings call to deliver one of its most aggressive capital deployment signals in years, raising its 2026 capital budget for the second time this year and announcing an additional $100 billion investment in Arizona, bringing total commitments there to $265 billion. CEO C.C. Wei said the expansion will add roughly four more fabs covering both front-end logic at 2-nanometer and below and advanced packaging, and that the decision reflects "strong collaboration and support from our leading U.S. customers and the U.S. federal, state and city governments."
CapEx Keeps Climbing, and Management Won't Rule Out More
TSMC now expects full-year 2026 capital expenditures of $60 billion to $64 billion, up from the $56 billion figure flagged in April and well above the original $52 billion to $56 billion range given in January. CFO Wendell Huang told UBS analyst Sunny Lin that the company would not provide multi-year CapEx guidance similar to what it offered during the 2021 super-cycle, but was unusually direct about the trajectory: "Last time, we said our CapEx in the next 3 years will be significantly higher than the CapEx in the past 3 years. Now the CapEx in the next 3 years will be even more significantly higher than the past 3 years." Wei added that part of the increase reflects tool cost inflation, not just incremental demand, saying plainly, "now we buy the tools with inflation price."
Roughly 70% to 80% of the 2026 budget is earmarked for advanced process technologies, with about 10% for specialty nodes and 10% to 20% for advanced packaging, testing and mask-making combined. Management declined to break out packaging capital spending separately despite a request from Goldman Sachs' Evelyn Yu, with Wei noting that bottlenecks shift unpredictably between front-end and back-end tooling, including a recent squeeze on testers.
Revenue Guidance Raised Again as Demand-Supply Gap Widens
TSMC now expects full-year 2026 revenue growth of "slightly above 40%" in U.S. dollar terms, an upgrade from prior commentary, driven by what Wei called "extremely robust" AI-related demand. Third-quarter revenue guidance of $44.6 billion to $45.8 billion implies 37% year-over-year growth at the midpoint. When Deutsche Bank's Robert Sanders pushed for a specific quantification of how far unconstrained demand for 3-nanometer and below exceeds supply, suggesting a range of 30% to 50%, Wei declined to confirm a number but acknowledged, "the gap is very big."
Wei was similarly evasive but revealing when asked by Morgan Stanley's Charlie Chan whether the company's five-year AI accelerator revenue CAGR guidance, previously mid-to-high 50s percent, has moved higher. "Let me give you not a number, but it's stronger and stronger and stronger," Wei said, adding that the company does not know how to quantify it because the trajectory keeps increasing. He offered a similarly candid explanation of how the company filters aggressive customer forecasts into a capacity plan: "I believe every customer tells me the truth, everyone. You put all the truths together, it's not the truth... because all the customers are very aggressive. That's the CEO's job. CEO's got to be aggressive." TSMC is reportedly cross-checking data center construction progress, rack deployment and power availability to ensure chips shipped are not simply parked in customer inventory.
Agentic AI Revives the CPU as a TSMC Growth Driver
One of the more consequential structural points from the call was Wei's framing of Agentic AI as a tailwind not just for accelerators but for CPUs, a segment some investors had assumed was ceding share to custom silicon. "The emergence of Agentic AI is leading to a resurgence in the role of CPUs in AI data centers, which drives more silicon demand in addition to AI accelerators," Wei said, noting that regardless of whether customers pursue x86, ARM-based or RISC-V architectures, "they are almost all TSMC's customers." This dynamic, combined with strong leading-edge demand, is one of the factors management cited behind the CapEx increase and the raised full-year outlook.
A14 Node Progressing Ahead of Schedule, with A13 and A12 Derivatives Confirmed
TSMC provided unusually detailed disclosure on its next-generation A14 node, the second generation of nanosheet transistor technology and the intended successor to N2. Versus N2, A14 is expected to deliver a 10% to 15% speed improvement at equivalent power, or a 25% to 30% power improvement at equivalent speed, alongside close to a 20% density gain. Internal product-like test vehicles have already demonstrated close to 90% device performance and close to 90% yield on 256-megabit SRAM test structures, and Wei said customer tape-out activity is "ongoing and ahead of schedule." Pre-production is slated for 2027 with volume production in 2028. The company also confirmed two derivative nodes, A13 and A12, both targeting volume production in 2029. A13 uses a 97% optical shrink to deliver more than 6% die area savings while remaining design-rule backward compatible with A14, easing IP migration. A12 introduces TSMC's superpower rail architecture onto the A14 platform. Wei framed the entire A14 family as a potential replay of the N2 node's unusually long commercial life, saying the company believes "A14 and its derivative technologies will propel our A14 family to be an even larger and long-lasting node for TSMC than N2, just like 2-nanometer technology is a larger and longer-lasting node than 3-nanometer."
Margin Trajectory: N2 Ramp and Overseas Dilution Are Real, but Temporary Headwinds
Second-quarter gross margin came in at 67.7%, up 150 basis points sequentially and slightly ahead of guidance, aided by cost improvement efforts and marginally higher utilization, partly offset by dilution from overseas fabs. Third-quarter gross margin guidance of 66% at the midpoint reflects a 3 to 4 percentage point drag from the steep ramp of 2-nanometer capacity, which management expects to persist through the second half. Separately, the company reiterated that overseas fab dilution will run 2 to 3 percentage points in early stages of ramp, widening to 3 to 4 percentage points in later stages as the scale of international expansion grows. Management continues to guide toward a long-term corporate gross margin of 53% or higher despite these pressures, leaning on cost improvement, productivity gains and cross-node capacity optimization to offset the drag.
Wei Addresses Competition From Samsung and Intel Head-On
Asked directly by Morgan Stanley's Charlie Chan about competitive threats from Samsung Foundry, flush with memory profits, and Intel, backed by U.S. government policy support, Wei was unusually candid: "One of my competitors in South Korea, they make a huge amount of money, and I'm jealous about it. And the other one in the U.S., they got a very strong U.S. government support. We also got the government support, by the way, although we don't announce it." He argued that switching foundry partners is not a low-friction decision, comparing the process to buying groceries: "Choosing a technology, ramping it up is not buying milk from 7-Eleven... you need to understand the technology, utilize it using the test chip, work together, prepare the capacity and ramp it up. That's why I would say it takes about 5 years." Wei identified technology, manufacturing execution and customer trust as TSMC's enduring competitive moat. On advanced packaging, Wei was notably unconcerned about Intel's EMIB-T gaining traction, framing it as capacity relief rather than a threat. "Our packaging capacity is so tight that now it's limited by customers' growth," he said, adding that TSMC "welcomes" alternatives that free up front-end wafer demand, which remains the larger share of its business. He also drew a sharp distinction between front-end and back-end competitive dynamics, telling Bank of America's Haas Liu that packaging traction from competitors does not translate into front-end wafer risk: "If they are the same, then you can expect ASE to become a front-end competitor also. It's two different things."
Mature Nodes: Shortage Is Narrow, Confined to Power Management and Image Sensors
Management pushed back on the notion of a broad mature-node recovery. Wei said shortages are concentrated in power management ICs, given AI data centers' power needs, and CMOS image sensors used for environmental sensing feeding AI systems, both often built on nodes like 0.18-micron or 90-nanometer. Outside those pockets, he said, "the consumer product is not in high demand... other segment is not so strong demand," reinforcing that TSMC's mature-node strategy remains selective, prioritizing higher value-added and strategic segments such as automotive and industrial applications through its JASM Japan and ESMC Germany fabs rather than chasing commodity volume.
Customer Concentration and Financing: No Change in Posture
Asked by Arete's Jim Fontanelli whether rising customer concentration among top AI customers posed a risk, Wei rejected the framing, attributing revenue growth to a broadening set of new AI entrants rather than dependence on a shrinking core. He also confirmed TSMC has no plans to follow some customers into direct financing or equity investment arrangements with their own downstream customers, saying the current business model is working "smoothly and successfully" as is.